搜索资源列表
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
wb_sdram_ctrl.tar
- Generic Wishbone R3 compliant SDRAM controller written in Verilog
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
sdram_src
- 基于FPGA的读写控制，sdram，简单易懂，verilog代码描述-FPGA-based read and write control, sdram, easy to understand, verilog code Descr iption
SDRAM_Verilog
- 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
sdram_mdl
- 基于SDRAM的读写调试试验，使用verilog语言编写，经过调试。-SDRAM-based literacy commissioning tests, using verilog language, through debugging.
sdram_5
- SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog descr iption, including top-level design, testbench code, an accurate descr iption of
SDRAM_96M
- 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
sdram_top
- 使用FPGA实现SDRAM逻辑控制器，适用于各种型号的FPGA-SDRAM control by verilog
ALTERA_FPGA_SDRAM
- 使用ALTERA的FPGA控制SDRAM的verilog程序-Use ALTERA s FPGA to control SDRAM s verilog program
5_Gray_Mean_Filter
- 均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有： （1）带PLL的全局时钟管理模块 system_ctrl_pll.v （2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig （3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565 （4）SDRAM数据交互控制器Sdram_Control_2Port （5）VGA时序
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)